From Python to hardware: real-time classical co-processing with PennyLane, Backline, and AMD

Moving from quantum research and development to production-grade execution is one of the most significant challenges facing quantum platform builders today — across quantum computing, networking, and sensing.

The challenge today? Quantum is never purely quantum. Just as a live band relies on hidden stage infrastructure (the "backline") to make a performance possible, quantum processors depend on highly performant classical computing working in perfect lockstep. While high-level Python frameworks like PennyLane provide an accessible entry point for quantum algorithm design, fault-tolerant quantum computing (FTQC) relies heavily on classical processing, requiring different classical accelerators and tiers of latency. In particular, real-time quantum error correction (QEC) requires extremely tight, microsecond feedback loops with CPUs, GPUs, FPGAs, and ASICs.

Catalyst — PennyLane's quantum compiler — was our first step in providing the software infrastructure to tackle this challenge. It utilizes the LLVM toolchain to capture and compile full quantum-classical workflows directly from Python, executing them close to bare-metal hardware. Yet, the programmability of these accelerators remains a major bottleneck. We need a way to orchestrate these strict, microsecond-latency hardware components directly from the Python interface where our applications are defined.

That is why, in collaboration with AMD, we're excited to announce Backline, an open platform for compilation and low-latency execution. By dynamically connecting quantum workloads to the right classical engine, this platform serves as a comprehensive development kit for the entire quantum ecosystem — from quantum computing to quantum sensing.

An open platform for the quantum community

Backline is a heterogeneous compilation fabric built natively within the open-source PennyLane platform and the Catalyst compiler. Designed to directly solve critical bottlenecks for quantum hardware, Backline is an openly available platform that is accessible and easily translated for cross-modality use.

With PennyLane and Backline, anyone can write a QEC encoder or decoder from Python, test it with meaningful quantum algorithms, and immediately deploy it for near-real-time prototyping on actual classical and quantum hardware — while supporting the need to drop through abstractions and write increasingly optimized and low-level code.

Key features include:

• Single-digit microsecond latency: With an under 3-microsecond end-to-end latency loop, Backline can effectively support the tight co-processing required for advanced QEC backup decoding by treating CPUs and GPUs as highly responsive, low-latency execution endpoints.

• Python-native: With Backline, you can write everything from Python. For example, use Python-based libraries like Triton and Gluon to write highly optimized GPU kernels for quantum coprocessing. You can also choose to connect pre-compiled libraries and functions for use with Backline, alongside high-level quantum application logic — easily jumping through abstraction layers without switching frameworks.

• Infrastructure agnostic by design: Different hardware platforms have drastically different requirements for error correction, utilizing classical accelerators from across the ecosystem. Backline leverages the expansive compilation tools of the LLVM ecosystem, and supports CPUs, GPUs, FPGAs, and custom devices from any hardware vendor.

• Scale from R&D to production: Backline leverages standard CPUs to deliver low-latency compute for workloads that do not strictly require heavy parallel GPU processing. This approach directly bypasses global GPU supply constraints and specialized systems that mandate shared CPU/GPU memory, and allows immediate prototyping. As you move towards production, progressively include consumer-grade and enterprise GPUs, FPGAs, and ASICs — all from the same software environment.

To see Backline in action, check out our demo, where we deploy a QEC application entirely from Python — scaling from local prototyping with CPUs, to low-latency remote hardware execution with FPGAs, GPUs, and Triton.

Pushing the limits

To ensure we can accurately measure the overheads of our design, we ran internal benchmarks to determine the floor latency of the ecosystem using heterogeneous hardware. Our results show a fast ~4.4 microsecond end-to-end latency looping between an AMD Versal™ Premium Series VPK120 FPGA (using the ERNIC™ IP block), an RDMA NIC, an AMD Instinct™ MI210 GPU, and back.

Furthermore, we achieve a mean-time to CPU of just ~2.3 microseconds — well within the latency requirements for quantum systems. This benchmarking — powered by an AMD Ryzen™ Threadripper™ Pro workstation — confirms that Backline can effectively support the synchronous co-processing tier required for advanced QEC decoding, whether you require GPUs or CPUs.

Performance benchmarking results from an FPGA ERNIC to workstation and back over ≈ 10⁶ samples. The FPGA uses the hardware handshake to lower the latency floor in the receiving end. Warm-up data is executed for the first round to ensure the hardware is stable before gathering data.

For more details on the performance and benchmarking, make sure to check out our technical paper.

Under the hood

Backline operates as a dynamic heterogeneous compiler and runtime environment explicitly engineered to sit natively within PennyLane and its Catalyst compiler. At its core, the architecture orchestrates complex quantum-classical workflows through a unified pipeline, utilizing MLIR and LLVM to heterogeneously compile to different devices.

Because different tasks require different execution speeds, Backline is designed to support multiple tiers of operational latency:

By providing a vendor-agnostic, Python-native path to heterogeneous execution, Backline drastically reduces the reliance on specialized C++ and hardware expertise, while maintaining the rigorous performance standards required for the next generation of fault-tolerant quantum computers. Ultimately, by seamlessly connecting quantum workloads to the right classical engine, this open architecture serves as a foundational development kit to power the future of the entire quantum ecosystem.

How to get started

Backline is available today. Head over to our GitHub repository, check out the tutorials, and dive into the documentation to start building.

• Learn more: Check out more details over on the AMD blog, and take a deeper dive with the Backline whitepaper.

• Start building: Install Backline and deploy a QEC application entirely from Python in our demo — scaling from local prototyping with CPUs, to low-latency remote hardware execution with FPGAs, GPUs, and Triton.

• Explore the technology: Read the Backline paper to get a technical overview of the infrastructure and performance.

Take PennyLane, Catalyst, and Backline for a spin wherever you have CPUs, GPUs, and FPGAs — from laptops, to supercomputing centers, to the lab — and deploy your quantum applications.

Interested in getting in touch with us? Simply head over to our GitHub repository and check out the ongoing work and join in on the development. Or pop over to the PennyLane discussion forum to let us know how you are using PennyLane, Backline, and Catalyst in your workflows.

And if you are as excited as we are, make sure to sign up for the PennyLane newsletter for the latest PennyLane features and updates!

Instinct, Ryzen, ERNIC, Versal, and Threadripper are trademarks of Advanced Micro Devices, Inc.