1. Compilation/

  2. Parity Table

Parity Table

The parity table PTP_T describes the phase factor in the phase polynomial intermediate representation. Technically, the parity table on its own is not an intermediate representation as it further requires the phase angles α\boldsymbol{\alpha} and parity matrix PP to describe (CNOT, RZR_Z) circuits (phase polynomials),

∣x⟩=e−iα2(1−2⋅PTx)∣Px⟩.|\boldsymbol{x}\rangle = e^{-i \frac{\boldsymbol{\alpha}}{2} \left(1 -2 \cdot P_T \boldsymbol{x} \right)} |P \boldsymbol{x}\rangle.

Sometimes, the phase factor α2(1−2⋅PTx)\frac{\boldsymbol{\alpha}}{2} \left(1 -2 \cdot P_T \boldsymbol{x} \right) itself is called the phase polynomial, which adds confusion to the terminology. We refer to phase polynomial intermediate representation for a full overview.

Inputs

  • (CNOT, RZR_Z) circuit with nn qubits and mm RZR_Z gates

Outputs

  • m×nm \times n binary matrix PTP_T with (PT)ij∈{0,1}(P_T)_{ij} \in \{0, 1\}

Example

Collecting the phase polynomial description by going through an example circuit and noting the current parities at each point of the circuit. Image taken from [1].

We go through each gate of the circuit and note down its action on the binary input state ∣x1,x2,x3,x3⟩|x_1, x_2, x_3, x_3\rangle. A CNOT gate adds the control value onto the target value. A RZR_Z gate collects the current parity, which is the logical value of that qubit. E.g. the first CNOT alters the first qubit value to x1⊕x2x_1 \oplus x_2. The corresponding parity that we collect at the first RZR_Z gate is (1,1,0,0)(1, 1, 0, 0), as we have n=4n=4 qubits in total, and its angle θ1\theta_1. We continue doing so throughout the circuit and collect the parities θ1(x1⊕x2)\theta_1 (x_1 \oplus x_2), θ2(x1⊕x2⊕x3)\theta_2 (x_1 \oplus x_2 \oplus x_3), and θ3(x1⊕x3⊕x4)\theta_3 (x_1 \oplus x_3 \oplus x_4), which we can summarize in the corresponding parity table

PT=(110011101011),P_T = \begin{pmatrix}1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 \end{pmatrix},

and angle vector θ=(θ1,θ2,θ3)\boldsymbol{\theta} = (\theta_1, \theta_2, \theta_3).

The overall accumulated phase of the circuit is given by

12θ⋅(1−2PTx)=12(θ1θ2θ3)⋅(1−2(110011101011)(x1x2x3x4)).\begin{align*} & \frac{1}{2} \boldsymbol{\theta} \cdot \left( 1- 2 P_T \boldsymbol{x} \right) \\ =& \frac{1}{2} \begin{pmatrix}\theta_1 \\ \theta_2 \\ \theta_3 \end{pmatrix} \cdot \left( 1- 2 \begin{pmatrix}1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 \end{pmatrix} \begin{pmatrix}x_1\\ x_2 \\ x_3 \\ x_4 \end{pmatrix} \right). \end{align*}

Typical usage

Parity tables are utilized in the phase polynomial intermediate representation for (CNOT, RZR_Z) circuits.

References

[1] "Phase polynomials synthesis algorithms for NISQ architectures and beyond", Vivien Vandaele, Simon Martiel, Timothée Goubault de Brugière arXiv:2104.00934, 2021

Cite this page

@misc{PennyLane-ParityTable,
    title = "Parity Table",
    author = "Korbinian Kottmann",
    year = "2025",
    howpublished = "\url{https://pennylane.ai/compilation/parity-table}"
}

Page author(s)

Korbinian Kottmann

Korbinian Kottmann

Quantum simulation & open source software